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Chapter 7: IP Core Interfaces 7–29

Cyclone V Hard IP for PCI Express

December 2013 Altera Corporation Cyclone V Hard IP for PCI Express

User Guide

Interrupts for Root Ports

Table 7–9 describes the signals available to a Root Port to handle interrupts.

Completion Side Band Signals

Table 7–9 describes the signals that comprise the completion side band signals for the

Avalon-ST interface. The Cyclone V Hard IP for PCI Express provides a completion

error interface that the Application Layer can use to report errors, such as

programming model errors. When the Application Layer detects an error, it can assert

the appropriate

cpl_err

bit to indicate what kind of error to log. The Hard IP sets the

appropriate status bits for the errors in the Configuration Space, and automatically

sends error messages in accordance with the PCI Express Base Specification. Note that

the Application Layer is responsible for sending the completion with the appropriate

completion status value for non-posted requests. Refer to Chapter 14, Error Handling

for information on errors that are automatically detected and handled by the Hard IP.

app_msi_func[2:0]

Indicates which function is asserting an interrupt with 0 corresponding to function 0, 1

corresponding to function 1, and so on.

app_int_sts_vec[7:0]

Level active interrupt signal. Bit 0 corresponds to function 0, and so on. Drives the INTx

line for that function. The core maps this status to INT A/B/C/D according to each

function’s

Interrupt_Pin

all sources, and generates INT MSGs on the rising/falling edges of the wire-ORed result.

The core logs the

tl_app_int_sts_vec

status in each functions’ PCI Status register.

Table 7–8. Interrupt Signals for Endpoints (Part 2 of 2)

Signal I/O Description

1 2 ... 122 123 124 125 126 127 128 129 130 131 132 ... 287 288

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