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100 www.xilinx.com Virtex-5 FPGA Integrated Endpoint Block
UG197 (v1.5) July 22, 2009
Appendix A: Integrated Endpoint Block Attributes
R
BAR1ADDRWIDTH
Integer Specifies BAR 1 address width. Valid settings are:
0: 32 bits wide
1: 64 bits wide
When 64-bit addressing is selected, the BAR
occupies both the BAR1 and BAR2 registers.
BAR2ADDRWIDTH
Integer Specifies BAR 2 address width. Valid settings are:
0: 32 bits wide
1: 64 bits wide
When 64-bit addressing is selected, the BAR
occupies both the BAR2 and BAR3 registers.
BAR3ADDRWIDTH
Integer Specifies BAR 3 address width. Valid settings are:
0: 32 bits wide
1: 64 bits wide
When 64-bit addressing is selected, the BAR
occupies both the BAR3 and BAR4 registers.
BAR4ADDRWIDTH
Integer Specifies BAR 4 address width. Valid settings are:
0: 32 bits wide
1: 64 bits wide
When 64-bit addressing is selected, the BAR
occupies both the BAR4 and BAR5 registers.
Because BAR5 must always be 32-bits wide, there is
no BAR5ADDRWIDTH attribute.
BAR0PREFETCHABLE
Boolean Specifies BAR 0 memory region is prefetchable.
Valid settings are:
TRUE: prefetchable
FALSE: not prefetchable
BAR1PREFETCHABLE
Boolean Specifies BAR 1 memory region is prefetchable.
Valid settings are:
TRUE: prefetchable
FALSE: not prefetchable
BAR2PREFETCHABLE
Boolean Specifies BAR 2 memory region is prefetchable.
Valid settings are:
TRUE: prefetchable
FALSE: not prefetchable
BAR3PREFETCHABLE
Boolean Specifies BAR 3 memory region is prefetchable.
Valid settings are:
TRUE: prefetchable
FALSE: not prefetchable
BAR4PREFETCHABLE
Boolean Specifies BAR 4 memory region is prefetchable.
Valid settings are:
TRUE: prefetchable
FALSE: not prefetchable
Table A-7: Integrated Endpoint Block Attributes (Continued)
Attribute Name Type Description
- Virtex-5 FPGA 1
- Integrated Endpoint Block 1
- Revision History 3
- VC1*, LOWPRIORITYVCCOUNT 4
- Table of Contents 5
- About This Guide 9
- Additional Documentation 10
- Additional Support Resources 11
- Typographical Conventions 11
- Preface: About This Guide 12
- Block Overview 13
- Memory Requirements 15
- Use Models 15
- Chapter 2 17
- Transaction Layer 18
- Data Link Layer 19
- Physical Layer 19
- Physical Layer Lane Module 20
- Clock Frequency 21
- Integrated 22
- Endpoint Block 22
- Transmit 28
- Channels 29
- Channel Ready 29
- Channel Select 29
- Transmit Framing 29
- Framing Errors 30
- DWORD Enables 30
- Transmit Handshake 30
- UG197_c2_04_030607 31
- Receive Framing 32
- Receive Handshake 32
- UG197_c2_06_111906 34
- Management Interface 37
- UG197_c2_08_082406 38
- Block RAM Interface 40
- RX and TX Buffer Capacity 41
- Retry Buffer Size 41
- Transceiver Interface 42
- Power Management Interface 45
- Registers 53
- Table 2-19: MSI Registers 55
- Reserved Registers 56
- Chapter 3 63
- Chapter 4 65
- Configuration Requests 66
- Transaction Ordering 67
- Interrupt Handling 68
- INTERRUPTDISABLE output: 69
- Error Detection 70
- Error Reporting 74
- Message Tags 76
- Phantom Function Support 76
- Lane Width 77
- Lane Reversal 77
- Workaround 78
- Appendix A 91
- TOTALCREDITS attributes are 92
- Initial Flow Control Credits 93
- Extended Capabilities 94
- The offset to the next PCI 105
- Contains the offset of 105
- UG197 (v1.5) July 22, 2009 108
- Glossary 109
- Function 112
- Hot plug 112
- Hot swap 112
- Isochronous data transfer 112
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